The present invention relates to an integrated circuit (hereinafter called IC) package, and more particularly to a flip chip mounting structure of a plastic ball grid array package.
In recent years, the flip chip bonding technique, in which a bare chip is directly mounted on a substrate by the face down process, has been improved as the semiconductor package is miniaturized at high density. There succeedingly appears portable telephones, each mounting a small package, so called CSP (chip size/scale package), having the approximately same size as the bare chip. The development of the CSP has rapidly been proceeded with the market requirement.
FIG. 7 shows steps for manufacturing an FC-PBGA (flip chip plastic ball grid array).
The step (a) shows a bonding step of a flip chip. In the step (a), a wafer having projected electrodes is cut into respective IC chips by dicing.
Flux is attached on the projected electrodes 2 on an IC chip 1 and the electrodes are mounted on bonding pads (not shown) formed on a circuit substrate 4. The IC chip 1 is secured to the circuit substrate 4 by reflowing the projected electrodes 2.
In the step (b), a sealing resin is put on the surface of the circuit substrate 4 and poured in the space between the IC chip 1 and the circuit substrate 4 by the capillary phenomenon to form a sealing resin 7. Thus, an IC mounting device 14 is formed. The IC mounting device is improved in resistivity to humidity and in resistivity to fatigue which is caused by the difference in line expansion coefficient between the IC chip 1 and the circuit substrate 4.
Thereafter, the sealing resin 7 is hardened by heat curing.
At the step (c), solder balls 11 are mounted on external electrode patterns 10, and secured thereto by reflowing the solder balls to form external solder electrodes 12 (step (d)).
In recent years, the IC chip becomes large in size, and accordingly the sealing resin is not sufficiently injected in the space between the IC chip and the circuit substrate. Consequently, there is formed voids in the sealing resin, which reduces the reliability of the IC mounting device.
Japanese Patent Publication 2607877 discloses a method for removing the voids by reducing the pressure of air surrounding IC chip.
FIG. 8 shows steps of the pressure reduction.
In the step (a), although the sealing resin 7 is poured in the space between the IC chip 1 and the circuit substrate 4 by the capillary phenomenon a void 6 is formed in the resin 7. The formation of void 6 is caused by various conditions such as the quality of resin, the size of the IC chip, conditions of the surface of the circuit substrate, and method of resin injection.
In the step (b), the IC mounting package 14 is put in a pressure reduced space, so that air in the void 6 is discharged from the sealing resin, thereby removing the void.
At the step (c), the sealing resin 7 is heated to be hardened.
FIG. 9 shows steps of an experiment for removing a void. In the experiment a glass chip is used for observing a void.
At steps (a, b), a void 6a generates in the sealing resin 7 between a glass chip 13 and the circuit substrate 4 at a central portion of the package 14.
At steps (c, d), the pressure of the ambient air of the package is reduced, so that the volume of the void increases.
Steps (e, f) show a condition where the pressure is further reduced, thereby the volume is more increased.
At steps (g, h), the air in the void 6 is discharged from the sealing resin 7, so that the void 6 disappears.
From the experiment it has been found that the void is not moved to a side of the package by pressure reduction, but the void gradually becomes large, and the air in the void spouts from the sealing resin when the void reaches the peripheral wall, thereby the void is compressed by the sealing resin to be disappeared.
The plastic ball grid array (PBGA) is standardized as MO-151 by the JEDEC (Joint Electron Device Engineering Council).
FIG. 10 is a plan view showing a PBGA having 5.times.5 grids, wherein positions of external electrode patterns 10 and positions of through-holes 14 each of which is formed in the circuit substrate 4 for connecting patterns on the surface and the underside of the circuit substrate 4.
In order to improve the electrical performance of the package, it is desirable to position the through-holes 14 a half-grid-pitch apart from the external electrode pattern 10.
The IC chip 1 is disposed at a central position of the package. As shown in FIG. 7, the pattern of the PBGA for the flip chip is approximately symmetrical with respect to an imaginary center line passing the center of the IC chip 1. In particular, the pattern in the central area is perfectly symmetrical. As a result, voids generated in a central zone are positioned in the central area.
In the conventional package, the position of each void generated in the sealing resin injection step irregularly changes at every package. The void generated in the central area becomes large by the pressure reduction. At last, the air pressure in the void balances with the pressure of the sealing resin so that the void does not break the outside wall of the resin. Thus, the void remains in the sealing resin. The moisture in the void and the stress of the void decrease the reliability of the package.